1. Field of the Invention
The present invention relates to a low latency transmission device, method and program in a semiconductor system for realizing decentralization of memory access loads.
2. Description of the Related Art
Conventionally, in order to decentralize memory access loads in a semiconductor chip circuit, a semiconductor system circuit having a hierarchical memory which includes organically combined memories of different access speeds has been proposed in consideration of both of the cost and the processing performance. Especially in order to solve the problem that load are centralized in a bus, research and development has been performed for decentralizing traffics into a plurality of transmission routes by means of a network in a semiconductor chip circuit, i.e., a network on chip (hereinafter in this specification, referred to as the “NoC”).
In this specification, a semiconductor system in which an NoC is used to decentralize buses and a plurality of rewritable memories such as DRAMs, SRAMs or the like are connected to the NoC is assumed.
In order to realize decentralization of memory access loads which can follow requests for memory access changing moment by moment in such a semiconductor system, it is necessary to determine both of a memory on which data is to be stored and a transmission route from a bus master (e.g., CPU or DSP) to the memory. Conventionally, technologies for allowing the bus master to select an optimum memory and technologies for selecting the transmission route have been developed separately.
One conventional method for determining the memory on which the data is to be stored is a round robin method, by which processing is assigned sequentially in the order of requests. As a method for determining the transmission route from the bus master to the memory, an efficient method of transmission on a network on chip has been proposed. Specifically, since the transmission routes are networked by use of relay devices (routers), a plurality of transmission routes can be selected for use. Therefore, technologies for efficiently using a plurality of routes to solve the problem of crowding of a bus have been published.
For example, Japanese Patent No. 3816531 discloses a technology for selecting routes for transmission on a network of mutually connected multiprocessors. According to the technology described in Japanese Patent No. 3816531, it is assumed that a plurality of routes can be selected. When there is no response within a certain time period on a route on which a packet has been transmitted, one of a plurality of predefined routes is selected in conformity to the distribution of predefined selection probability for each route, and thus the packet is re-transmitted. Namely, according to this technology, a transmission route is selected based on the result of monitoring the transmission quality of the routes on a network on a semiconductor system.
According to the conventional technologies, it is attempted to improve the transmission efficiency by adjusting the memory on which the data is to be stored and the transmission route from the bus master to the memory separately. In the future, more efficient and low latency network transmission needs to be realized. According to the conventional technologies, no transmission method has been considered in the case where requested transmission delay characteristics are different traffic by traffic.
Specifically, the conventional method for determining the memory on which the data is to be stored is a round robin method, and therefore the memory on which the data is to be stored is not assigned in accordance with the memory access load changing moment by moment. In the case of, for example, video data, the code amount of which is significantly changed in terms of time in accordance with the contents, the access load is significantly different among the memories to which the data is assigned and thus the decentralization of memory access loads does not effectively function.
On a network of a network on chip, a traffic for which low latency transmission is requested, and also a traffic for which low latency transmission is not requested, are both existent. For example, processing for which high responsiveness is needed, such as a user operation, and a traffic for which responsiveness is not needed, such as depiction of a background, are both existent. In the case where such traffics are existent on the same network, the traffic for which the request level for low latency is low influences the traffic for which the request level for low latency is high due to mutual interference of the traffics. Therefore, a method for determining a memory on which the data is to be stored and a transmission route, in consideration of the difference in the traffic characteristic (in the above example, traffic rate or request level for low latency) is needed.
The present invention has an object of realizing a more efficient and low latency network transmission in consideration of the difference in the traffic characteristics and the memory access loads changing moment by moment.